1. Field of the Invention
The present invention relates to a phase adjusting circuit for a demodulator used for a facsimile, a modem, or the like.
2. Description of the Related Art
In a facsimile, a modem, or the like using telephone lines for the transmission of signals, analog carrier signals are phase-modulated by digital signals by phase shift keying (PSK) before being transmitted through the telephone lines. Such phase-modulated transmitted signals are often demodulated through a phase locked loop (PLL) circuit where carrier signals generated in the PLL circuit are compared with the transmitted signals so as to be synchronized with them.
FIG. 6 shows a conventional phase adjusting circuit incorporating such a PLL circuit for a demodulator used for a facsimile, a modem or the like.
An analog signal transmitted to the demodulator is first input to an analog signal processing circuit 21 where the signal is subjected to necessary processings including narrowing the frequency band. The processed analog signal is then sent to an analog sampling/holding circuit 22 where the signal is sampled at a predetermined sampling interval for the following step of analog-digital (A/D) conversion and the sampled signal level is temporarily held. A Nyquist interval is adopted for the sampling interval. The Nyquist interval is the maximum interval required to satisfy the sampling theorem. According to the sampling theorem, information on an original signal will not be lost in so far as the signal is sampled at a frequency of at least twice the frequency within the frequency bandwidth thereof. The signal sampled by the analog sampling/holding circuit 22 is then sent to an A/D converter 23 where the signal is quantized and converted into a digital signal.
The digital signal converted by the A/D converter 23 is then sent to a digital signal processing circuit 24. The digital signal processing circuit 24 detects any phase error in the digital signal sent from the A/D converter 23 with regard to a carrier signal generated from a carrier signal generating circuit 25. When a phase error is detected by the digital signal processing circuit 24, the sampling interval in the analog sampling/holding circuit 22 is adjusted through a timing adjusting circuit 26, so as to synchronize the phase at the sampling point of the carrier signal with that of the transmitted signal.
The operation of such a phase adjusting circuit will be described with reference to FIG. 7.
A transmitted signal S.sub.11 output from the analog signal processing circuit 21 is assumed to be a cosine wave having a frequency f as shown in FIG. 7. The frequency f is a modulated carrier-signal frequency. The sampling interval at the analog sampling/holding circuit 22 is therefore the interval T represented by the equation of: EQU T=1/2 f (1)
The carrier signal generating circuit 25 generates a carrier signal S.sub.c which is also a cosine wave having the same frequency f as the modulated carrier-signal frequency. The analog sampling/holding circuit 22 effects sampling when the phase angle of the carrier signal S.sub.c is 0.degree. or 180.degree..
Assume that the analog sampling/holding circuit 22 samples the transmitted signal S.sub.11 at the phase angle of 45.degree. at time t.sub.1 in order to output a sampled signal S.sub.12. A time corresponding to one sampling interval is required until the sampled signal S.sub.12 output from the analog sampling/holding circuit 22 is quantized by the A/D converter 23 and output therefrom as a digital signal S.sub.13 to the digital signal processing circuit 24. When the digital signal processing circuit 24 detects the phase error of 45.degree. (one-fourth of the interval T) in the digital signal S.sub.13, the timing adjusting circuit 26 instructs the analog sampling/holding circuit 22 to shorten the next sampling interval to three-fourths of the interval T. As a result, the sampling interval between time t.sub.2 and time t.sub.3 is shortened so as to adjust the phase error. Thus, though the transmitted signal S.sub.11 is still sampled at the phase angle of 225.degree. at time t.sub.2, it can be sampled at the phase angle of 0.degree. or 180.degree. at and after time t.sub.3. Since the output of the digital signal S.sub.13 from the A/D converter 23 is delayed by one sampling interval behind the sampling time, it is at and after time t.sub.4 that the phase of the digital signal S.sub.13 synchronizes with that of the transmitted signal S.sub.11.
In recent years, a technique of combining an over-sampling system and a delta-sigma (.DELTA..SIGMA.) modulation system has been developed so that the frequency distribution of quantized noise can be dispelled to a high-level range beyond the frequency band of a transmitted signal, thereby improving the resolution of the signal at phase adjustment.
In the over-sampling system, however, the sampling is performed at such a high frequency for example as much as 32 or 64 times the Nyquist frequency, and thus the sampling interval is very short. Accordingly, when the over-sampling system is adopted for the demodulator, the phase adjustment through the PLL circuit as described above is not possible with the conventional phase adjusting circuit as shown in FIG. 6 unless a device operable at a considerably high speed is used. Even when such a high-speed device is used, the over-sampling system requires an additional step of filtering a digital signal by a digital filter after the A/D conversion so as to narrow the frequency band of the signal within the range where digital signal processing is possible. This step causes a time delay and results in degrading the performance of the PLL circuit.